1. Field of the Invention
The present invention relates to an organic electroluminescent light emitting unit driving method.
2. Description of the Related Art
Heretofore, there have been display elements including a light emitting unit, and display apparatuses including such a display element. For example, display elements including an organic electroluminescent light emitting unit which takes advantage of the electroluminescence of an organic material (hereafter, simply abbreviated to “organic EL display element” in some cases) have attracted attention as display elements capable of bright luminescence according to low-voltage DC driving.
In the same way as liquid crystal display apparatuses, for example, with display apparatuses including an organic EL display element (hereafter, simply abbreviated to “organic EL display apparatus” in some cases) as well, the simple matrix method and the active matrix method have been widely applied. The active matrix method has a shortcoming in that the configuration becomes complicated, but has an advantage in that the brightness of an image can be improved, or the like. The organic EL display elements driven by the active matrix method include not only a light emitting unit configured of an organic layer or the like including a light emitting layer but also a driving circuit used for driving the light emitting unit.
Driving circuits configured of two transistors and one capacitor unit (referred to as “2Tr/1C driving circuit”) have been widely used as a circuit used for driving an organic electroluminescent light emitting unit (hereafter, simply abbreviated to “light emitting unit” in some cases), for example, according to Japanese Unexamined Patent Application Publication No. 2007-310311. This 2Tr/1C driving circuit is, as shown in FIG. 2, configured of two transistors of a writing transistor TRW, and a driving transistor TRD, and further, configured of a single capacitor unit C1. Here, the other source/drain region of the driving transistor TRD makes up a second node ND2, and the gate electrode of the driving transistor TRD makes up a first node ND1.
As shown in the timing chart in FIG. 5, preprocessing used for threshold voltage cancellation processing is executed at period TP(2)1. That is to say, a first node initializing voltage VOfs (e.g., 0 volt) is applied to the first node ND1 from a data line DTL via the writing transistor TRW which has been set to an on state by a signal from a scanning line SCL. Thus, the potential of the first node ND1 becomes VOfs. Also, a second node initializing voltage VCC-L (e.g., −10 volts) is applied to the second node ND2 from a power supply unit 100 via the driving transistor TRD. Thus, the potential of the second node ND2 becomes VCC-L. The threshold voltage of the driving transistor TRD is represented with Vth (e.g., 3 volts). The potential difference between the gate electrode and the other source/drain region (hereafter, referred to as “source region” in some cases) of the driving transistor TRD becomes Vth or more, and the driving transistor TRD goes to an on state.
Next, the threshold voltage cancellation processing is executed at period TP(2)2. Specifically, while the on state of the writing transistor TRW is maintained, the voltage of the power supply unit 100 is switched from the second node initializing voltage VCC-L to a driving voltage VCC-H (e.g., 20 volts). As a result thereof, the potential of the second node ND2 is changed toward a potential obtained by subtracting the threshold voltage Vth of the driving transistor TRD from the potential of the first node ND1. That is to say, the potential of the second node ND2 in a floating state increases. Subsequently, upon the potential difference between the gate electrode and the source region of the driving transistor TRD reaching Vth, the driving transistor TRD goes to an off state. In this state, the potential of the second node ND2 becomes approximately (VOfs−Vth).
Subsequently, the writing transistor TRW is set to an off state at period TP(2)3. Subsequently, the voltage of a data line DTL is set to a voltage equivalent to a video signal [video signal (driving signal, brightness signal) VSig—m used for controlling brightness at a light emitting unit ELP].
Next, writing processing is executed at period TP(2)4. Specifically, a scanning line SCL is set to a high level, thereby setting the writing transistor TRW to an on state. As a result thereof, the potential of the first node ND1 increases to the video signal VSig—m.
Now, let us say that the value of the capacitor unit C1 is set to a value c1, the value of the capacitance CEL of the light emitting unit ELP is set to a value CEL, and the value of parasitic capacitance between the gate electrode and the other source/drain region of the driving transistor TRD is set to cgs. When the potential of the gate electrode of the driving transistor TRD is changed from VOfs to VSig—m (>VOfs), the potentials of both ends of the capacitor unit C1 (in other words, the potentials of the first node ND1 and second node ND2) are changed as a general rule. Specifically, charge based on the amount of change (VSig—m−VOfs) in the potential of the gate electrode of the driving transistor TRD (i.e., the potential of the first node ND1) is distributed to the capacitor unit C1, the capacitance CEL of the light emitting unit ELP, and the parasitic capacitance between the gate electrode and the other source/drain region of the driving transistor TRD. Therefore, in the case that the value cEL is a sufficiently great value as compared to the values c1 and cgs, the change in the potential of the other source/drain region (second node ND2) of the driving transistor TRD based on the amount of change (VSig—m−VOfs) in the potential of the gate electrode of the driving transistor TRD is small. In general, the value cEL of the capacitance CEL of the light emitting unit ELP is greater than the value c1 of the capacitor unit C1, and the value cgs of the parasitic capacitance of the driving transistor TRD. Therefore, description will be made without considering the change in the potential of the second node ND2 caused due to change in the potential of the first node ND1 for the sake of explanatory convenience. Note that the driving timing chart shown in FIG. 5 is illustrated without considering the change in the potential of the second node ND2 caused due to change in the potential of the first node ND1.
With the above operation, the video signal VSig—m is applied to the gate electrode of the driving transistor TRD in a state in which the voltage VCC-H is applied to one of the source/drain regions of the driving transistor TRD from the power supply unit 100. Therefore, as shown in FIG. 5, the potential of the second node ND2 increases at period TP(2)4. The increase amount ΔV (potential corrected value) of this potential will be described later. When assuming that the potential of the gate electrode (first node ND1) of the driving transistor TRD is Vg, and the potential of the other source/drain region (second node ND2) is Vs, in the case that the increase amount ΔV of the potential of the second node ND2 is not taken into consideration, the value of the Vg and the value of the Vs are as follows. The potential difference between the first node ND1 and second node ND2, i.e., difference value Vgs between the gate electrode and the other source/drain region serving as a source region of the driving transistor TRD, can be represented with the following Expression (A).Vg=VSig—m Vs=VOfs−Vth Vgs≅VSig—m−(VOfs−Vth)  (A)
That is to say, the Vgs obtained at the writing processing as to the driving transistor TRD depends on only the video signal VSig—m used for controlling the brightness of the light emitting unit ELP, the threshold voltage Vth of the driving transistor TRD, and the voltage VOfs used for initializing the potential of the gate electrode of the driving transistor TRD, but is not linked to the threshold voltage Vth-EL of the light emitting unit ELP.
Next, mobility correction processing will be described briefly. With the above operation, mobility correction processing is executed along with the writing processing, wherein the potential of the other source/drain region of the driving transistor TRD (i.e., the size of mobility or the like) is changed according to the property of the driving transistor TRD (e.g., the potential of the second node ND2).
As described above, the video signal VSig—m is applied to the gate electrode of the driving transistor TRD in a state in which the voltage VCC-H is applied to one of the source/drain regions of the driving transistor TRD from the power supply unit 100. Here, as shown in FIG. 5, the potential of second node ND2 increases at period TP(2)4. As a result thereof, in the case that the value of the mobility μ of the driving transistor TRD is great, the increase amount ΔV (potential corrected value) of the potential at the source region of the driving transistor TRD increases, and in the case that the value of the mobility μ of the driving transistor TRD is small, the increase amount ΔV (potential corrected value) of the potential at the source region of the driving transistor TRD decreases. The potential difference Vgs between the gate electrode and the source region of the driving transistor TRD is obtained by Expression (A) being changed to the following Expression (B). Note that the entire time (t0) of period TP(2)4 should be determined as a design value beforehand at the time of design of an organic EL display apparatus.Vgs≅VSig—m−(VOfs−Vth)−ΔV  (B)
The threshold voltage cancellation processing, writing processing, and mobility correction processing are completed according to the above operations. Subsequently, at the commencement of the subsequent period TP(2)5, the writing transistor TRW is set to an off state by a signal from a scanning line SCL, thereby setting the first node ND1 to a floating state. One of the source/drain regions (hereafter, referred to as “drain region” as appropriate) of the driving transistor TRD is in a state in which the voltage VCC-H is applied thereto from the power supply unit 100. Therefore, as a result of the above-described, the potential of the second node ND2 increases, and the same phenomenon as with a so-called bootstrap circuit is generated at the gate electrode of the driving transistor TRD, and accordingly, the potential of the first node ND1 also increases. The potential difference Vgs between the gate electrode and the source region of the driving transistor TRD holds the value of Expression (B). Also, a current flowing into the light emitting unit ELP is a drain current Ids that flows from the source region to the drain region, of the driving transistor TRD. If we say that the driving transistor TRD operates ideally at a saturation region, the drain current Ids can be represented with the following Expression (C). The light emitting unit ELP emits light with the brightness corresponding to the value of the drain current Ids. Note that a coefficient k will be described later.
                                                        Ids              =                            ⁢                              k                ·                μ                ·                                                      (                                                                  V                        gs                                            -                                              V                        th                                                              )                                    2                                                                                                        =                            ⁢                              k                ·                μ                ·                                                      (                                                                  V                                                  Sig                          ⁢                                                                                                          ⁢                          _                          ⁢                                                                                                          ⁢                          m                                                                    -                                              V                        Ofs                                            -                                              Δ                        ⁢                                                                                                  ⁢                        V                                                              )                                    2                                                                                        (        C        )            
Next, let us say that the period TP(2)5 shown in FIG. 5 is set as an emitting period, and between the commencement of the period TP(2)6′ and the next emitting period is set as a non-emitting period. Such a non-emitting period is provided, whereby afterimage blurring due to active matrix driving is reduced, and moving image quality can further be improved.
The operation of the 2Tr/1C driving circuit of which the overview has been described above will also be described later in detail.